Energy Optimizations of SRAM and STT-RAM Multi-Level Caches from 1995-2016
نویسنده
چکیده
This paper reviews the cache designs of processors from 1995 until today, studying the development of multi-level caches, especially the chosen device technology, and how it has evolved with the needs of multi-core processors. It is found that SRAM, while fast, has the drawbacks of high energy use and a constant need for power, making it power for storage over an extended time. STT-RAM enters the scene in the mid 2000’s, offering a low energy, low leakage alternative to SRAM. However, it is found to be slower, so research is done to speed it up. The additional research done on STT-RAM to reduce its latency allows it to become a mainstream technology. Finally, eDRAM makes its debut in the cache device technology realm, offering a fast, volatile memory with high scalability and capacity. Keywords—Last-Level Cache(LLC), SRAM, Spin Transfer Torque RAM (STT-RAM), eDRAM, Write-Back (WB), WriteThrough (WT), Firefly, Instructions Per Clock (IPC), Single Event Upsets (SEUs), Multi-Bit Upsets (MBUs), Bit Upset Vulnerability
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